1. Fundamental Theory of Buck-Boost DC-DC Conversion
In power electronics design, the buck-boost converter represents a canonical switch-mode power supply (SMPS) topology capable of delivering an output voltage that can be higher, lower, or equal in absolute magnitude to the input supply voltage. Unlike classic step-down (buck) or step-up (boost) architectures, the buck-boost topology accommodates battery discharge curves where the chemical cell voltage begins above the required system rail and subsequently declines below it as capacity is depleted.
The standard classical topology is the inverting buck-boost converter, which produces a negative output voltage relative to circuit ground using a single controlled active switch (MOSFET), a passive freewheeling diode (or synchronous secondary MOSFET), an energy storage inductor, and an output filter capacitor. During the switch conduction phase (\(t_{on} = D \cdot T_{sw}\)), the inductor is connected directly across the DC input source. Energy accumulates in the inductor's magnetic core as the flux density ramps up linearly, while the diode is reverse-biased, isolating the output capacitor and load. During the switch turn-off interval (\(t_{off} = (1 - D) \cdot T_{sw}\)), the collapsing magnetic field reverses the inductor's terminal voltage, forward-biasing the freewheeling diode and discharging stored electromagnetic energy into the output filter capacitor and external load.
2. Core Mathematical Derivations & Governing Equations
To design an efficient, thermally resilient switch-mode power converter, power stage magnetics and semiconductor components must be synthesized through rigorous volt-second balance and charge-balance relationships. Under steady-state Continuous Conduction Mode (CCM), the net volt-seconds applied across the inductor over one complete switching period \(T_{sw} = 1 / f_{sw}\) must equate to zero:
$$\int_0^{T_{sw}} v_L(t) \, dt = (V_{in}) \cdot D \cdot T_{sw} + (-V_{out} - V_D) \cdot (1 - D) \cdot T_{sw} = 0$$Solving for the nominal duty ratio \(D\) while factoring in power stage efficiency \(\eta\) and diode forward drop \(V_D\) gives:
$$D = \frac{V_{out} + V_D}{V_{in} \cdot \eta + V_{out} + V_D}$$The average inductor current \(I_{L,avg}\) exceeds the DC load current \(I_{out}\) because the inductor transfers energy to the output network only during the turn-off interval \((1 - D)\):
$$I_{L,avg} = \frac{I_{out}}{1 - D}$$The peak-to-peak inductor current ripple \(\Delta I_L\) is specified as a fraction \(r\) (the inductor ripple ratio, typically selected between \(0.20\) and \(0.40\)) of the average inductor current:
$$\Delta I_L = r \cdot I_{L,avg} = r \cdot \frac{I_{out}}{1 - D}$$Applying Faraday's Law during the switch ON-time yields the required power stage inductance \(L\):
$$L = \frac{V_{in} \cdot D}{\Delta I_L \cdot f_{sw}} = \frac{V_{in} \cdot D \cdot (1 - D)}{r \cdot I_{out} \cdot f_{sw}}$$The peak inductor current \(I_{L,pk}\) and root-mean-square (RMS) current \(I_{L,rms}\), critical for core saturation checking and copper wire loss calculations, are expressed as:
$$I_{L,pk} = I_{L,avg} + \frac{\Delta I_L}{2}$$ $$I_{L,rms} = \sqrt{I_{L,avg}^2 + \frac{\Delta I_L^2}{12}}$$Because the output filter capacitor must supply the full load current during the switch conduction time \(D \cdot T_{sw}\), output capacitance requirements are notably more stringent than those of a standard buck converter. The minimum capacitance \(C_{out}\) to guarantee an output voltage ripple no greater than \(\Delta V_o\) is:
$$C_{out,min} = \frac{I_{out} \cdot D}{\Delta V_o \cdot f_{sw}}$$3. Empirical Design Benchmark Table for SMPS Inductors
The following engineering data table provides standard magnetic core material selections, permeability values, saturation flux densities, and recommended operational frequency bands for switch-mode converter design:
| Core Material | Composition | Initial Permeability (\(\mu_i\)) | Saturation Flux \(B_{sat}\) (T) | Core Loss at 100 kHz | Optimal Frequency Range |
|---|---|---|---|---|---|
| Sendust (Kool M\(\mu\)) | Fe-Si-Al alloy powder | 60: 125 | 1.05 T | Low | 50 kHz: 500 kHz |
| High Flux | 50% Ni, 50% Fe alloy | 14: 160 | 1.50 T | Moderate | 20 kHz: 300 kHz |
| MPP (Molypermalloy) | 79% Ni, 17% Fe, 4% Mo | 14: 300 | 0.75 T | Lowest | 100 kHz: 1.5 MHz |
| Iron Powder (-26 mix) | Pure distributed air gap Fe | 75 | 1.40 T | High | 10 kHz: 100 kHz |
| Power Ferrite (MnZn) | N87 / 3C90 sintered ceramic | 2000: 3000 (gapped) | 0.38: 0.49 T | Very Low | 100 kHz: 2.0 MHz |
4. Right-Half-Plane Zero (RHPZ) and Feedback Compensation
A crucial dynamic characteristic of Continuous Conduction Mode (CCM) buck-boost and boost topologies is the presence of an inherent Right-Half-Plane (RHP) Zero in the power stage control-to-output transfer function \(G_{vd}(s)\). The frequency of this zero is calculated as:
$$\omega_{RHPZ} = \frac{R_{load} \cdot (1 - D)^2}{D \cdot L} \quad \implies \quad f_{RHPZ} = \frac{R_{load} \cdot (1 - D)^2}{2\pi \cdot D \cdot L}$$In classical control theory, an ordinary left-half-plane zero contributes \(+20\text{ dB/decade}\) of gain slope and \(+90^\circ\) of phase lead, improving stability. Conversely, an RHP zero boosts loop gain by \(+20\text{ dB/decade}\) while introducing a severe \(-90^\circ\) phase lag. If the closed-loop crossover frequency \(f_c\) approaches \(f_{RHPZ}\), the system experiences uncontrollable regenerative oscillation. Consequently, power supply design guidelines enforce the rule that loop crossover frequency must be kept below:
$$f_{cross} \le \frac{1}{3} \text{ to } \frac{1}{5} f_{RHPZ}$$5. Worked Engineering Case Study: Automotive Step-Up/Down Supply
Design Specification: 12V Nominal to 24V Auxiliary Rail
An automotive telemetry computer requires a regulated \(V_{out} = 24\text{ V}\) rail delivering \(I_{out} = 2.5\text{ A}\) (\(60\text{ W}\)). The automotive battery fluctuates between \(V_{in,min} = 9\text{ V}\) during cold cranking and \(V_{in,nom} = 13.8\text{ V}\). The controller operates at \(f_{sw} = 150\text{ kHz}\) with an estimated efficiency \(\eta = 88\%\), Schottky diode drop \(V_D = 0.5\text{ V}\), ripple current ratio \(r = 0.30\), and peak-to-peak output ripple limit \(\Delta V_o \le 50\text{ mV}\).
Step 1: Compute Maximum Operating Duty Cycle (Worst-Case Low Input)
At \(V_{in} = 9\text{ V}\):
$$D = \frac{24 + 0.5}{(9 \times 0.88) + 24 + 0.5} = \frac{24.5}{7.92 + 24.5} = \frac{24.5}{32.42} \approx 0.7557 \text{ (75.6\%)}$$Step 2: Average Inductor Current and Target Current Ripple
$$I_{L,avg} = \frac{I_{out}}{1 - D} = \frac{2.5}{1 - 0.7557} = \frac{2.5}{0.2443} = 10.233\text{ A}$$ $$\Delta I_L = r \times I_{L,avg} = 0.30 \times 10.233\text{ A} = 3.07\text{ A}$$Step 3: Inductance Calculation
$$L = \frac{V_{in} \cdot D}{\Delta I_L \cdot f_{sw}} = \frac{9 \times 0.7557}{3.07 \times 150{,}000} = \frac{6.8013}{460{,}500} \approx 14.77 \times 10^{-6}\text{ H} \approx 15\text{ }\mu\text{H}$$Step 4: Inductor Peak Current and Component Voltage Stress
$$I_{L,pk} = 10.233 + \frac{3.07}{2} = 11.77\text{ A}$$ $$V_{sw,max} = V_{in,max} + V_{out} + V_D = 16\text{ V} + 24\text{ V} + 0.5\text{ V} = 40.5\text{ V}$$A power MOSFET rated for at least \(60\text{ V}\) breakdown with low \(R_{DS(on)}\) and an inductor with a saturation current rating \(I_{sat} \ge 14\text{ A}\) are selected to provide adequate operating margin.
Step 5: Minimum Output Filter Capacitance
$$C_{out,min} = \frac{I_{out} \cdot D}{f_{sw} \cdot \Delta V_o} = \frac{2.5 \times 0.7557}{150{,}000 \times 0.050} = \frac{1.8893}{7500} \approx 251.9\text{ }\mu\text{F}$$A parallel combination of three \(100\text{ }\mu\text{F}\), \(35\text{ V}\) low-ESR polymer aluminum electrolytic capacitors shunted by two \(10\text{ }\mu\text{F}\) X7R ceramic capacitors satisfies both the capacitive bulk requirement and high-frequency ESR ripple suppression.
6. Frequently Asked Questions
What is the primary difference between inverting and four-switch non-inverting buck-boost converters?
An inverting buck-boost converter reverses the polarity of the DC output with respect to ground and employs only two power switches (one active transistor and one diode). A four-switch synchronous non-inverting buck-boost converter utilizes four power MOSFETs (two half-bridges) and an inductor. It preserves positive voltage polarity and delivers superior efficiency (>96%) by operating dynamically as a pure buck converter when \(V_{in} \gg V_{out}\), a pure boost converter when \(V_{in} \ll V_{out}\), and in 4-switch buck-boost mode only when input and output voltages are nearly identical.
Why is the inductor ripple current ratio (r) typically chosen between 0.2 and 0.4?
Selecting \(r\) between 0.20 and 0.40 provides an optimal trade-off between magnetic component volume and power losses. A lower ripple ratio (\(r < 0.2\)) requires a large, bulky inductor with higher DCR (winding resistance), increasing copper losses and slowing closed-loop transient response. A higher ripple ratio (\(r > 0.4\)) produces severe AC peak currents, excessive core hysteresis and eddy-current losses, and demands much larger output capacitors to attenuate voltage ripple.
How does Right-Half-Plane (RHP) zero affect the compensation loop of a buck-boost converter in CCM?
In Continuous Conduction Mode, when the control loop demands higher output voltage by suddenly increasing duty cycle \(D\), the immediate short-term effect is a reduction in the switch turn-off time \((1 - D)\), temporarily decreasing the energy delivered to the load until inductor current ramps up. This phenomenon creates a Right-Half-Plane zero that increases open-loop gain by \(+20\text{ dB/decade}\) while degrading loop phase by \(-90^\circ\). To prevent severe phase margin erosion and instability, loop bandwidth must be restricted to less than one-third to one-fifth of the RHP zero frequency.
How is the minimum critical inductance (L_crit) calculated to maintain Continuous Conduction Mode (CCM)?
Continuous Conduction Mode requires that the instantaneous inductor current does not drop to zero at any point during the cycle. At the CCM/DCM boundary, peak-to-peak ripple current \(\Delta I_L\) equals twice the average inductor current. For a minimum operating load current \(I_{out,min}\), critical inductance is calculated as:
$$L_{crit} = \frac{V_{in} \cdot D}{2 \cdot I_{L,avg,min} \cdot f_{sw}} = \frac{V_{in} \cdot D \cdot (1 - D)}{2 \cdot I_{out,min} \cdot f_{sw}}$$